1. Field of the Invention
This invention relates to semiconductor device technology, and in particular to a wiring structure, a semiconductor device and their fabrication methods which reduce the wiring capacitance in circuits where narrow gaps exist between wires.
Priority is claimed on Japanese Patent Application No. 2007-160342, filed on Jun. 18, 2007, the content of which is incorporated herein by reference.
2. Description of Related Art
Miniaturization of the wiring structures in integrated circuits is advancing in keeping with the large-scale integration of semiconductor devices. Because of these advancements, the gap between wires in a wiring structure becomes unusually narrow, and leakage currents between adjacent wires flow easily and wiring capacitance becomes great.
Methods exist which reduce the dielectric constant of a wiring interlayer insulating film for the purpose of reducing wiring capacitance. Generally, in order to achieve reductions of the wiring capacitance, an air gap structure having air gaps in wiring interlayer insulating films, a damascene structure configured by conducting wires and via holes (hereinafter they may be referred to as “vias”), a film which has doped carbon or fluorine in silicon, and the like, are used.
Japanese Unexamined Patent Application First Publication No 2000-349329, for example, discloses a memory element of diode construction in which a semiconductor porous microcrystal layer composed of nanocrystals is formed on a semiconductor substrate.
Japanese Unexamined Patent Application, First Publication No. 2003-45325 and Japanese Unexamined Patent Application, First Publication No. 2004-319523 disclose a method for depositing a microcrystal layer composed of nanometer size fine particles on a plurality of concave parts on an n-type silicon substrate using the PCVD (Plasma Chemical Vapor Deposition) method.
However, the air gap in conventional air gap structures is generally of spherically-shaped pores, and the effect is limited to the portion where the wire space is a minimum. When an oxide film is used, the relative dielectric constant of the portion of a wide space is in the range of 3.9-4.2 and cannot be changed with conventional technology.
When forming vias, the vias can be misaligned with the underlying wiring layer, abutting the air gap, so that metal of the via fills the air gap causing a short with adjacent vias. In order to avoid this shortcoming, it is necessary to establish a joint margin for the wire and via. This causes the problem that the wire pitch becomes large.
In a damascene structure, after forming a low dielectric constant film having fine pores, the groove structure of the via or wire is fabricated. In this case, there is a problem that moisture used during the fabrication process is absorbed within the low dielectric constant film.
When using a film of carbon or fluorine-doped silicon, the following problems exist: the working strength of the film becomes weak, the wet etch rate is reduced because of the damage incurred during processing, and the dielectric constant increases due to the absorption of moisture within the film.